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| SN54/74LS259 8-BIT ADDRESSABLE LATCH The SN54/ 74LS259 is a high-speed 8-Bit Addressable Latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and also a 1-of-8 decoder and demultiplexer with active HIGH outputs. The device also incorporates an active LOW common Clear for resetting all latches, as well as, an active LOW Enable. 8-BIT ADDRESSABLE LATCH LOW POWER SCHOTTKY * * * * * * Serial-to-Parallel Conversion Eight Bits of Storage With Output of Each Bit Available Random (Addressable) Data Entry Active High Demultiplexing or Decoding Capability Easily Expandable Common Clear CONNECTION DIAGRAM DIP (TOP VIEW) 16 J SUFFIX CERAMIC CASE 620-09 1 VCC 16 C 15 E 14 D 13 Q7 12 Q6 11 Q5 10 Q4 9 16 1 N SUFFIX PLASTIC CASE 648-08 1 Ao 2 A1 3 A2 4 Q0 5 Q1 6 Q2 7 Q3 8 GND 16 1 D SUFFIX SOIC CASE 751B-03 PIN NAMES LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 5 (2.5) U.L. A0, A1, A2 D E C Q0 to Q7 Address lnputs Data Input Enable (Active LOW) Input Clear (Active LOW) input Parallel Latch Outputs (Note b) 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 10 U.L. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA FAST AND LS TTL DATA 5-433 SN54/74LS259 LOGIC DIAGRAM E 14 D 13 1 A0 2 A1 A2 3 15 C VCC = PIN 16 GND = PIN 8 = PIN NUMBERS 4 5 6 7 9 10 11 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FUNCTIONAL DESCRIPTION The SN54 / 74LS259 has four modes of operation as shown in the mode selection table. In the addressable latch mode, data on the Data line (D) is written into the addressed latch.The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one-of-eight decoding or demultiplexing mode, the MODE SELECTION E L H L H C H H L L MODE Addressable Latch Memory Active HIGH Eight-Channel Demultiplexer Clear C E D A0 LHX X LLL L LLH L LLL H LLH H *** *** *** *** *** LLH H HHX H H H H * * * * * H H I L L L * * * * * L L I H L H * * * * * L H X L L H H A1 X L L L L * * * * * H X L L L L * * * * * H H A2 X L L L L Q0 L L H L L addressed output will follow the state of the D input with all other inputs in the LOW state. In the clear mode all outputs are LOW and unaffected by the address and data inputs. When operating the SN54 / 74LS259 as an addressable latch, changing more then one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The truth table below summarizes the operations. TRUTH TABLE PRESENT OUTPUT STATES Q1 L L L L H Q2 L L L L L Q3 L L L L L * * * * * L Q4 L L L L L Q5 L L L L L Q6 L L L L L Q7 L L L L L MODE Clear Demultiplex H X L L L L L QN-1 L H QN-1 QN-1 L L L L L H Memory QN-1 QN-1 L H QN-1 QN-1 QN-1 QN-1 QN-1 Addressable Latch X = Don't Care Condition L = LOW Voltage Level H = HIGH Voltage Level QN-1 = Previous Output State * * * * * QN-1 QN-1 L H H H H H QN-1 QN-1 FAST AND LS TTL DATA 5-434 SN54/74LS259 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current -20 - 0.4 - 100 36 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Turn-Off Delay, Enable to Output Turn-On Delay, Enable to Output Turn-Off Delay, Data to Output Turn-On Delay, Data to Output Turn-Off Delay, Address to Output Turn-On Delay, Address to Output Turn-On Delay, Clear to Output Min Typ 22 15 20 13 24 18 17 Max 35 24 32 21 38 29 27 Unit ns ns ns ns ns ns ns Test Conditions CL = 15 pF AC SET-UP REQUIREMENTS (TA = 25C, VCC = 5.0 V) Limits Symbol ts tW th th Input Setup Time Pulse Width, Clear or Enable Hold Time, Data Hold Time, Address Parameter Min 20 15 5.0 20 Typ Max Unit ns ns ns ns FAST AND LS TTL DATA 5-435 SN54/74LS259 AC WAVEFORMS D D tw E tw 1.3 V Q 1.3 V 1.3 V tPHL 1.3 V tPLH 1.3 V tPHL Q tPLH 1.3 V OTHER CONDITIONS: E = L, C = H, A = STABLE OTHER CONDITIONS: C = H, A = STABLE Figure 2. Turn-on and Turn-off Delays, Data to Output Figure 1. Turn-on and Turn-off Delays, Enable To Output and Enable Pulse Width A1 1.3 V 1.3 V D th(H) th(L) ts(L) 1.3 V A1 1.3 V 1.3 V E ts(H) tPHL Q1 1.3 V tPLH 1.3 V Q Q=D Q=D OTHER CONDITIONS: E = L, C = L, D = H OTHER CONDITIONS: C = H, A = STABLE Figure 3. Turn-on and Turn-off Delays, Address to Output Figure 4. Setup and Hold Time, Data to Enable C 1.3 V A tPHL ts E STABLE ADDRESS Q 1.3 V OTHER CONDITIONS: E = H Figure 5. Turn-on Delay, Clear to Output OTHER CONDITIONS: C = H Figure 6. Setup Time, Address to Enable (See Notes 1 and 2) NOTES: 1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is addressed and the other latches are not affected. 2. The shaded areas indicate when the inputs are permitted to change for predictable output performance. FAST AND LS TTL DATA 5-436 -A- Case 751B-03 D Suffix 16-Pin Plastic SO-16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751B 01 IS OBSOLETE, NEW STANDARD 751B 03. 16 9 -B1 8 P 8 PL 0.25 (0.010) M B M R X 45 G -TD 16 PL 0.25 (0.010) M C SEATING PLANE K T B S M F J A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 3.80 1.35 0.35 0.40 10.00 4.00 1.75 0.49 1.25 INCHES MIN MAX 0.386 0.150 0.054 0.014 0.016 0.393 0.157 0.068 0.019 0.049 1.27 BSC 0.19 0.10 0 5.80 0.25 0.25 0.25 7 6.20 0.50 0.050 BSC 0.008 0.004 0 0.229 0.010 0.009 0.009 7 0.244 0.019 Case 648-08 N Suffix 16-Pin Plastic -A16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: INCH. DIMENSION L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B" DOES NOT INCLUDE MOLD FLASH. 5. 6. ROUNDED CORNERS OPTIONAL. 648 01 THRU 07 OBSOLETE, NEW STANDARD 648 08. B 1 8 F S C -TK SEATING PLANE L H G D 16 PL 0.25 (0.010) M J M T A M DIM A B C D F G H J K L M S MILLIMETERS MIN MAX 18.80 6.35 3.69 0.39 1.02 19.55 6.85 4.44 0.53 1.77 INCHES MIN MAX 0.740 0.250 0.145 0.015 0.040 0.770 0.270 0.175 0.021 0.070 2.54 BSC 1.27 BSC 0.21 2.80 7.50 0 0.51 0.38 3.30 7.74 10 1.01 0.100 BSC 0.050 BSC 0.008 0.110 0.295 0 0.020 0.015 0.130 0.305 10 0.040 -A16 9 Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. -B1 8 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. C L 5. 620 01 THRU 08 OBSOLETE, NEW STANDARD 620 09. -TSEATING PLANE K E F D 16 PL 0.25 (0.010) M N G T A S M J 16 PL 0.25 (0.010) M T B S DIM A B C D E F G J K L M N MILLIMETERS MIN MAX 19.05 6.10 19.55 7.36 4.19 0.39 0.53 INCHES MIN MAX 0.750 0.240 0.770 0.290 0.165 0.015 0.021 1.27 BSC 1.40 1.77 0.050 BSC 0.055 0.070 2.54 BSC 0.23 0.27 5.08 7.62 BSC 0 0.39 15 0.88 0.100 BSC 0.009 0.011 0.200 0.300 BSC 0 0.015 15 0.035 FAST AND LS TTL DATA 5-437 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. FAST AND LS TTL DATA 5-438 |
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